`timescale 1ps/1ps
`include "./src/mips.v"

module Testbench();
    reg    clk ;
    reg    rst ;

    initial begin
        $dumpfile("wave.vcd");
        $dumpvars;
    end
    
    //instantiate module of mips
    Mips mips(clk, rst);

    //initialize test
    
    initial 
        begin
            clk <= 0 ;
            rst <= 1 ;
            #10 rst <= 0 ;
            // #200 rst <= 1 ; 
            // #10 rst <= 0 ; 
            #5000 $finish;
        end
            
    //周期
    always@(*)
    begin
         #20 clk<=~clk;
    end
       
    
endmodule 